The AD7569 is a complete, 8-bit, analog I/O system on a single monolithic
chip. The AD7569 contains a high speed successive approximation ADC with
2 μs conversion time, a track/hold with 200 kHz bandwidth, a DAC
and output buffer amplifier with 1 μs settling time. A temperature-
compensated 1.25 V reference provides a precision reference voltage for
the ADC and the DAC.
A choice of analog input/output ranges is available. Using a supply voltage
of +5 V, input and output ranges of zero to 1.25 V and zero to 2.5 V may
be programmed using the RANGE input pin. Using a ±5 V supply, bipolar
ranges of ±1.25 V or ±2.5 V may be programmed.
Digital interfacing is via an 8-bit I/O port and standard microprocessor
control lines. Bus interface timing is extremely fast, allowing easy
connection to all popular 8-bit microprocessors. A separate start convert line
controls the track/hold and ADC to give precise control of the sampling period.
The AD7569 provides everything necessary to interface a microprocessor to the
analog world. No external components or user trims are required, and the
overall accuracy of the system is tightly specified, eliminating the need to
calculate error budgets from individual component specifications.
Pin function description (the electronic diagram shows the pin numbers):
- <#178#>#math42##tex2html_wrap_inline891#<#178#> Analog ground for the DAC. Separate ground return
paths are provided for the DAC and ADC to minimize crosstalk.
- <#179#>#math43##tex2html_wrap_inline893#<#179#> Output voltage. #math44#VOUT is the buffered output
voltage from the AD7569 DAC. Four different output voltage ranges can be
achieved (see Table #tab:ranges#113>).
- <#180#>#math45##tex2html_wrap_inline896#<#180#> Negative supply voltage (-5 V for dual supply or 0 V
for single supply). This pin is also used with the RANGE pin to select the
different input/output ranges and changes the data format from binary
(#math46#VSS=0 V) to 2s complement (#math47#VSS=-5 V) (see Table
#tab:ranges#117>).
- <#118#>RANGE<#118#> Range selection input. This is used with the #math48#VSS
input to select the different ranges as per Table #tab:ranges#120>. The
range selected applies to both the analog input voltage of the ADC and the
output voltage from the DAC.
- <#181#>#math49##tex2html_wrap_inline901#<#181#> Reset input (active low). This is an
asynchronous system reset which clears the DAC register to all 0s and clears
the #math50##tex2html_wrap_inline903# line of the ADC (i.e., makes the ADC ready for new
conversion). In unipolar operation this input sets the output voltage to
0 V; in bipolar operation it sets the output to negative full scale.
- <#123#>DB0-DB7<#123#> Data bits. DB0 is the least significant bit.
- <#124#>DGND<#124#> Digital ground.
- <#182#>#math51##tex2html_wrap_inline905#<#182#> Write input (edge triggered). This is used in
conjunction with #math52##tex2html_wrap_inline907# to write data into the AD7569 DAC
register. Data is transferred on the rising edge of #math53##tex2html_wrap_inline909#.
- <#183#>#math54##tex2html_wrap_inline911#<#183#> Chip select input (active low). The device is
selected when this input is active. DB0-DB7 are in the high impedance state
when this input is high.
- <#184#>#math55##tex2html_wrap_inline913#<#184#> Read input (active low). This input must be
active to access data from the part. It is used in conjunction with the
#math56##tex2html_wrap_inline915# input.
- <#185#>#math57##tex2html_wrap_inline917#<#185#> Start conversion (edge triggered). This is used
when precise sampling is required. The falling edge of #math58##tex2html_wrap_inline919#
starts conversion and drives #math59##tex2html_wrap_inline921# low. The #math60##tex2html_wrap_inline923#
signal is not gated with #math61##tex2html_wrap_inline925#
- <#186#>#math62##tex2html_wrap_inline927#<#186#> BUSY status output (active low). When this pin
is active the ADC is performing a conversion. The input signal is held prior to
the falling edge of #math63##tex2html_wrap_inline929#.
- <#187#>#math64##tex2html_wrap_inline931#<#187#> INTERRUPT output (active low).
#math65##tex2html_wrap_inline933# going low indicates that the conversion is complete.
#math66##tex2html_wrap_inline935# goes high on the rising edge of #math67##tex2html_wrap_inline937# or
#math68##tex2html_wrap_inline939# and is also set high by a low pulse on
#math69##tex2html_wrap_inline941#.
- <#144#>CLK<#144#> A TTL compatible clock signal may be used to determine the ADC
conversion time. Internal clock operation is achieved by connecting a resistor
and capacitor to ground.
- <#188#>#math70##tex2html_wrap_inline943#<#188#> Analog ground for the ADC.
- <#189#>#math71##tex2html_wrap_inline945#<#189#> Analog input. Various input ranges can be selected
(see Table #tab:ranges#147>).
- <#190#>#math72##tex2html_wrap_inline947#<#190#> Positive supply voltage (+5 V).
Absolute maximum ratings:
#math73#VDD to AGNDDAC or AGNDADC -0.3 V, +7 V
#math74#VDD to DGND -0.3 V, +7 V
#math75#VDD to VSS -0.3 V, +14 V
#math76#AGNDDAC or AGNDADC to DGND ±5 V
Logic voltage to DGND -0.3 V, #math77#VDD+0.3 V
CLK input voltage to DGND -0.3 V, #math78#VDD+0.3 V
#math79#VOUT to AGNDDAC1 #math80#VSS -0.3V, VDD + 0.3V
#math81#VIN to AGNDADC #math82#VSS -0.3V, VDD + 0.3V
Power dissipation 450 mW
I did my utmost best to exclude all errors from the contents of the
ADDA10.ZIP archive. Because I am just like you only human, the described
circuit might not work or, even worse, cause damage to other equipment.
Nevertheless, I assume no liability for this. The only guarantee I can give
you is that my board2 functions up to expectation. Of course any suggestions
to improve the correctness and intelligibility of the description, diagrams
and software are much appreciated, as are experiences of other people who
built and used the circuit. These will have their impact on possible future
versions of the archive.
Jos Groot (InterNet: jos.groot@fel.tno.nl)
van de Wateringelaan 4
2274 CH Voorburg
The Netherlands